DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-6 ( Jun, 2014 ) | |||||||||
Paper Title |
Full Chip Level Implementation Of Reed Solomon Encoder | |||||||||
Author Name |
Amar Narayan, Sheetal Belaldavar, Venkateshappa | |||||||||
Affilition |
M.Tech Student, Dept. of ECE, MSEC, M.Tech Student, Dept. of ECE, MSEC, Associate Professor, Dept. of ECE, MSEC | |||||||||
Pages |
86-89 | |||||||||
Abstract |
Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage .The Reed-Solomon encoder takes a block of digital data and adds extra "redundant" bits. The number and type of errors that can be corrected depends on the characteristics of the Reed-Solomon code .The Reed-Solomon Encoder is used in many Forward Error Correction (FEC) applications and in systems where data are transmitted and subject to errors before reception. In this paper Full Chip level Implementation of Reed Solomon Encoder has been carried out. In Full Chip Level Implementation, in order to optimize the area of the design, SIPO and PISO shift registers are implemented and also the I/O pads, VDD and VSS pads are added in to the design. The timing, area and the power values which are obtained during Synthesis are as follows: Timing=0.0(Met), Area=9965.160037 and Power=2.33878mW respectively and the physical design steps such as Floor Planning, Placement, CTS, Routing and Verification are carried out in the design. | |||||||||
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