DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-6 ( Jun, 2014 ) | |||||||||
Paper Title |
Behavioral Modeling Of Sigma-Delta Modulator Non-Idealities With Two Step Quantization In Matlab/Simulink | |||||||||
Author Name |
Shashant Jaykar, Kuldeep Pande, Atish Peshattiwar, Abhinav Parkhi | |||||||||
Affilition |
Department of Electronics Engineering, Yeshwantrao Chavan College of Engineering, Nagpur, India | |||||||||
Pages |
42-46 | |||||||||
Abstract |
An architecture to simplify the circuit implementation of analog-to-digital (A/D) converter in a sigma-delta (ΣΔ) modulator is proposed. The two-step quantization technique is utilized to design architecture of ΣΔ modulator. The architecture is based on dividing the A/D conversion into two time steps for achieving resolution improvement without decreasing speed. The novel architecture is designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. Switched capacitor (SC) modulator performance is prone to various nonidealities, which affects overall circuit performance. In this paper a set of models are proposed which takes into account SC ΣΔ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (noise, finite dc gain, finite bandwidth, slew-rate and saturation voltages). Each nonidealities are modelled mathematically and their behaviour is verified using different analysis in MATLAB Simulink. Simulation results on a second-order SC ΣΔ modulator with two step quantization demonstrate the validity of the models proposed. | |||||||||
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