DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-5 ( May, 2014 ) | |||||||||
Paper Title |
Minimization Of Thd By Multilevel Inverters Using Digital Technique | |||||||||
Author Name |
Srikrishnan.B, S.Lakshmikanth Bharathi | |||||||||
Affilition |
B.E. Electrical & Electronics Engineering (Fourth year) Cauvery College Of Engineering & Technology Trichy, Tamilnadu, India | |||||||||
Pages |
1-4 | |||||||||
Abstract |
The cascaded multilevel inverter (CMLI) has gained much attention in recent years due to its advantages in high voltage and high power with low harmonics applications. A standard cascaded multilevel inverter requires n DC sources for 2n+1 levels at the output, where n is the number of inverter stages. This paper presents a topology to control cascaded multilevel inverter that is implemented with multiple DC sources to get 2 n+1 -1 levels. Without using Pulse Width Modulation (PWM) technique, the firing circuit can be implemented using flip-flop which greatly reduces the Total Harmonic Distortion (THD) and switching losses. To develop the model of a cascaded hybrid multilevel inverter, a simulation is done based on MATLAB/SIMULINK software. Their integration makes the design and analysis of a hybrid multilevel inverter more complete and detailed | |||||||||
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