DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-4 ( Apr, 2014 ) | |||||||||
Paper Title |
Area & Delay Efficient Adders For Arithmetic Applications | |||||||||
Author Name |
Ganesh Kumar V, Sridhar R, Gaffoor S A | |||||||||
Affilition |
Department of Electronics and Communication Engineering Panimalar Engineering College, Anna University, Chennai, India | |||||||||
Pages |
23-26 | |||||||||
Abstract |
As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. In this brief, we propose a new adder that outperforms all state-of- the art competitors and achieves the best area-delay tradeoff. The above advantages are obtained by using an overall area similar to the cheaper designs known in literature. The 64-bit version of the novel adder spans over 18.72 µm2 of active area and shows a delay of only nine clock cycles, that is just 36 clock phases. | |||||||||
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