DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-6 ( Jun, 2017 ) | |||||||||
Paper Title |
Design and Configuration of Low Phase Noise and Wideband Frequency Synthesizer | |||||||||
Author Name |
Bhargav Patel, Keyur Mahant, Alpeshvala, Killol Pandya | |||||||||
Affilition |
Electronics & Communication Engineering Department, CSPIT, Changa, India Charusat Space Research and Technology Center, CHARUSAT, Changa, India | |||||||||
Pages |
26-28 | |||||||||
Abstract |
PLL is used in a variety of frequency synthesis systems. The design and implementation of phase locked loop (PLL) based frequency synthesizer using Analog ADF5355 is presented. This PLL is used as a frequency synthesizer which generates stable frequency for the various applications. Reference frequency of 100MHz is applied from TCXO to generate frequency at 9.4GHz Keywords - PLL, Loop filter, Phase Frequency Detector, Frequency synthesizer, FPGA. | |||||||||
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