DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-6 ( Jun, 2017 ) | |||||||||
Paper Title |
VHDL Implementation of Bijective/Reversable Full Subtractor and Comparator using TR Gate | |||||||||
Author Name |
Sanjeev, Swathi, Swetha, Vinay | |||||||||
Affilition |
Electronics and Communication Engineering Department, PESIT-BSC | |||||||||
Pages |
7-9 | |||||||||
Abstract |
It is interesting to compare both reversible and conventional gates. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In the last years reversible logic functions has emerged as an important research area. Other fields such as low-power design, optical computing and quantum computing benefit directly from achieved improvements. This paper implements a subtractor and a 4 bit comparator using the TR gate. To implement the 4 bit comparator 8 TR gates are required while 2 TR gates are required to implement the subtractor. The comparator works on the subtraction algorithm and it is implemented using the full subtractors built using the TR gates. Reversible logic are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Keywords: TR gate, Comparator, Full Subtractor, Reversible logic | |||||||||
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