DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-4 ( Apr, 2017 ) | |||||||||
Paper Title |
Design of a High Speed Multiplier Less Radix 2^K FFT Architecture for High Rate OFDM Applications | |||||||||
Author Name |
Talluri Nirmala, M.Srikanth, M.Shanmukachaitanya | |||||||||
Affilition |
152W1D6812 GVR&S College of Engineering and Technology Asst.Prof. Dept.Of ECE GVR&S College of Engineering and Technology 3162W1D6806 GVR&S College of Engineering and Technology | |||||||||
Pages |
40-43 | |||||||||
Abstract |
In this paper, we propose the design of a high speed reconfigurable CORDIC based FFT architecture which is a key component in the Orthogonal Frequency Division Multiplexing modulation scheme. FFT has been used in the sub carier mapping layer which is main driving force in high rate WPANs. This proposed architecture consists of radix-22 where twiddle factor multiplications is optimized using pre processing steps.In particular,this generalized radix-2k FFT architecture uses only three multiplication unit for complex multiplications and to replace the multiplication units by shift and add units using CORDIC.Thus,the proposed architecture is built with reduced hardware requirements and less number of complex multiplications in computing FFT. The twiddle factor memory is also reduced thereby increasing the speed of the computation. Index Terms- FFT(Fast Fourier transform),radix-2k algorithm,CORDIC,CSD multiplication. | |||||||||
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