DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-4 ( Apr, 2017 ) | |||||||||
Paper Title |
Design and Implementation of Shortest Path and Fault tolerant algorithm in NOC | |||||||||
Author Name |
Shridhar S. Bilagi, Raymond Irudayaraj I., Ulaganathan J., Abdul Lateef Haroon P.S | |||||||||
Affilition |
Assistant Professors, Dept. Of ECE, BITM/RYMEC-Ballari-583104 | |||||||||
Pages |
56-59 | |||||||||
Abstract |
This paper describes an innovation scaling, dependability as became the main problem for network on chip (NOC). Numerous deficiencies tolerant steering calculations for NOC are produced to eliminate segments & gives solid transmission. In any case, proposed steering calculations don't give careful consideration to locate the most limited ways, which expands dormancy and force utilization. In this one, a shortcoming tolerant directing calculation utilizing new segment states dissemination technique in light of “Farthest Reachable Router (FRR)” is implemented. In this, calculation can decrease inactivity by identifying the limited paths among the source and destination switches. Tested simulation output confirms for the FRR directing calculation endure 50% shortcoming designs inside 3×3 and decrease inactivity by 16-44% contrasted & FON. Keywords - Network on chip (NOC), Node, Router, FRR | |||||||||
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