DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-3 ( Mar, 2017 ) | |||||||||
Paper Title |
Design and Simulation of Power Quality Circuit for Power Quality Improvement Using SVPWM Technique | |||||||||
Author Name |
N. Eashwaramma, J.Praveen | |||||||||
Affilition |
Dept. Of EEE, Research scholar JNTUA, A.P,INDIA Professor , Dept. Of EEE 3. Dr.M. Vijaya Kumar, Professor, Dept. Of EEE | |||||||||
Pages |
33-38 | |||||||||
Abstract |
The major power quality problems occurs in the distribution lines so these distribution lines will be distributed non standard voltage, current, frequency utility distribution Networks, sensitive loads and Critical commercial operation suffers from various types of power quality problems and huge losses of energy in the distribution lines. There are various form of power quality problems like Voltage sag, Voltage Swell, Harmonics distortion (THD), Flicker. Voltage sag and swell are fewer harmonic compared to the flicker. In this paper design nine level cascaded multilevel inverter (MLI) in the operation of dynamic voltage restorer (DVR) using Space Vector Pulse Width Modulation Technique (SVPWM) control technique will be used for voltage source converter. SVPWM can be utilize the dc voltage and generates the fever harmonics compared to other techniques .The work describes the DVR based on SVPWM provides voltage support to sensitive loads and will be simulated by using MATLAB/SIMULINK Software. Key Words- 9 level cascaded MLI, DVR, SVPWM, SAG, SWELL, Flickers, MATLAB / SIMULINK Software. | |||||||||
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