DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-4,Issue-9 ( Sep, 2016 ) | |||||||||
Paper Title |
Design of AES on FPGA Hardware | |||||||||
Author Name |
Shruti Shrivastava, A.Y.Kazi | |||||||||
Affilition |
P.G. Student, Department of Electronics Engineering, AISSMS’S COE, Pune Univeristy, Pune, Maharashtra (India) Department of Electronics Engineering, AISSMS’S COE, Pune Univeristy, Pune, Maharashtra (India) | |||||||||
Pages |
152-154 | |||||||||
Abstract |
Advanced Encryption Standard (AES) is the contemporary encryption standard. The Advanced Encryption standard approved by federal information processing standard (FIPS) defines the cryptographic algorithm that can be used to protect electronic data. The AES algorithm encrypt (encipher) and decrypt(decipher) information in a symmetric manner. Encryption converts data to an indistinct form called cipher text; and again decrypting the cipher text converts the data back into its readable form, called plaintext. The AES algorithm can use cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. Keywords— AES Encrption, FPGA, Algorithm. | |||||||||
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