DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Special Issue (2016) ( Sep, 2016 ) | |||||||||
Paper Title |
Asic Design Of CCD Clock Generator | |||||||||
Author Name |
Esakkimuthu M, Gyanendra Kumar Kashyap, Krishnam Prasad B, Siva Yellampalli | |||||||||
Affilition |
Student, Principal, Scientist/Engineer – SF, VTU Extension Centre, UTL Technologies Ltd, Yeshwanthpur, Bangalore Laboratory for Electo-Optics Systems (LEOS-ISRO) Peenya Industrial Estate, Bangalore | |||||||||
Pages |
11-15 | |||||||||
Abstract |
In this paper we present the design and implementation aspects in Application Specific Integrated Circuits (ASIC) of CCD Clock Generator (CCG). A Charge Coupled Device (CCD) is used as imaging sensor in various applications. The CCD requires sequence of clocks to acquire image. The designed CCG creates sequence of clocks to acquire video data from CCD in terms of analog voltage. The analog video signal is digitalized with the help of Analog to Digital Converter (ADC) on each sequence of pixel clocks synchronously. The CCG is designed to collect images up to 1k x 1k pixels (expandable). The designed CCG provides feature to operate the CCD in various modes like vertical charge transfer mode, horizontal charge transfer mode, binning mode, and flush mode. CCG is programmable and has shared Video RAM, Interface for Central Processing Unit (CPU), interface for Video ADC and inbuilt 1553 protocol controller. Keywords- ASIC, CCD, CCG, FPGA, CPU, DFT, GDS | |||||||||
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