DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
||||||||
Issue |
Volume-4,Issue-7 ( Jul, 2016 ) | |||||||||
Paper Title |
Functionality Verification Of Standard Cell Library | |||||||||
Author Name |
Kavya Shivashankar | |||||||||
Affilition |
EC Department NMAMIT NITTE, Mangalore | |||||||||
Pages |
147-148 | |||||||||
Abstract |
Standard cell library is intended to have all the digital cells (Most commonly used digital building blocks). Each cell will have different views like Layout, Schematic, Symbol, Verilog, Netlist etc. The scope of this project is to do the functionality verification of Verilog and Netlist. In this project the functionality verification of Verilog and HspiceNetlist by using mixed signal simulation tool COSIM is done. COSIM is basically a mixed signal simulation tool, where analog and digital simulation can be done in one go. The output of COSIM i.e., Netlist simulated and Verilog simulated graphical output will be compared and then result will be thrown out as PASS or FAIL.This flow is made as a generic tool using PERL so that it can be used to do the functionality verification of Verilog and Netlist of all the cells in a library and is independent of technology. Keywords— RTL, HDL, COSIM, PERL. | |||||||||
| View Paper | ||||||||||
