DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-4,Issue-6 ( Jun, 2016 ) | |||||||||
Paper Title |
Simulation Of Nanoscale Dual-Material Gate Double-Layer Gate- Stack Bulk Planar Junctionless Transistor | |||||||||
Author Name |
Neha U. Chaudhari, S. C. Wagaj, Snehal R. Mulmane | |||||||||
Affilition |
Electronics Engineering , JSPMs Rajashri Shahu College of Engineering,Tathwade, Pune,India. | |||||||||
Pages |
30-33 | |||||||||
Abstract |
A simulation study of analog and digital parameters of dual material gate bulk planar junctionless transistor are discussed. The characteristics are demonstrated and compared with DMG BPJLT and Single Material (conventional) Gate (SMG) BPJLT. The DMG BPJLT presents superior Subthreshold Swing (SS) and reduces Drain Induced Barrier Lowering (DIBL) as compared with SMG BPJLT. By adjusting the metal work functions; channel potential and electric field distribution along the channel can be controlled. Keywords— Bulk Planer Junctionless Transistor (BPJLT),junctionless transistor (JLT),Short Channel Effects(SCE). Dual material Date Bulk Planer Junctionless Transistor (DMG-BPJLT), single Material Gate (SMG) | |||||||||
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