DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-4,Issue-5 ( May, 2016 ) | |||||||||
Paper Title |
Implementation Of Fast Fourier Transform Using Verilog HDL | |||||||||
Author Name |
Anup Tiwari, Samir Kumar Pandey | |||||||||
Affilition |
Department of ECE, Jharkhand Rai University,Ranchi , Jharkhand, India Department of Mathematical Sciences, XIPT, Ranchi | |||||||||
Pages |
77-81 | |||||||||
Abstract |
The Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operations in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware’s like DSP. So a fine solution is to use dedicated hardware processor to perform efficient FFT working out at high sample rate, while the DSP could perform the less concentrated parts of the processing. Verilog implementation of floating point FFT with reduced generation logic is the proposed architecture, where the two inputs and two outputs of any butterfly can be exchanged hence all data and addresses in FFT dispensation can be reordered. Keywords— FFT, MAC, butterfly exchanging circuit, PGA, DSP’s. | |||||||||
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