DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-3,Issue-11 ( Nov, 2015 ) | |||||||||
Paper Title |
A Highly Linear Low Noise CMOS LNA For Wireless Communication Applications | |||||||||
Author Name |
Chinmay Deshpande, Savita R. Pawar | |||||||||
Affilition |
PG Student, MITAOE, Pune. Asst. Prof, Dept. of Electronics, MITAOE, Pune. | |||||||||
Pages |
11-14 | |||||||||
Abstract |
In this paper, the design of a highly linear wideband CMOS low-noise amplifier (LNA) for wireless communication applications ranging from 600 MHz to 3 GHz using 0.13-μm technology is described. Here, CMOS inverter based wideband LNA is used in this design. Input Impedance matching is achieved by using negative resistive feedback along with feed-forward topology. The proposed amplifier achieves wideband input matching with S11 of less than -10 dB for overall bandwidth range. The designed LNA demonstrates a 33--24dB voltage gain (S21), 1.6—1.9dB noise figure (NF) with IIP3 of +8.02dB. The design drains 13mA of current from 1.2v supply with power consumption of 15.6mW. Index Terms—CMOS inverter, Low noise, inductorless, Noise Figure, Noise cancelling, Wideband amplifiers. | |||||||||
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