DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-7 ( Jul, 2015 ) | |||||||||
Paper Title |
Design Of Fixed-Width Booth Multiplier Using MLCP In Fir Application | |||||||||
Author Name |
Abinaya M., Kashwan K. R. | |||||||||
Affilition |
Department of Electronics and Communication Engineering – PG, Sona College of Technology (Autonomous Institutions), Salem-636005, INDIA | |||||||||
Pages |
59-62 | |||||||||
Abstract |
Multiplier plays an important role in digital signal processing circuits. It requires considerable power and area. Normally a fixed width multiplier is used to reduce the power and area occupied by the multiplier on a chip. The proposed method consists of designing a fixed width multiplier using booth algorithm. It simplifies structure of multiplier to reduce power and improve performance of the circuit. Fixed width multiplier receives two numbers, each of n bit long and produces an n bit product. The direct truncation of least significant part of the product produces the large error in the resultant product if fixed width output is the requirement. This paper proposes a truncation error reducing logic that is multi-level conditional probability (MLCP) which considerably reduces truncation error. Index Terms— MLCP, booth multiplier, fixed width multiplier, truncation. | |||||||||
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