DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-5 ( May, 2015 ) | |||||||||
Paper Title |
Design Of Pass Gates Adder Circuit With Imprroved Performance On Power Constraint | |||||||||
Author Name |
Deepika Shahare, Ankita Kuhikar, Naheed Anjum | |||||||||
Affilition |
3 Students, Department of Electronics and Telecommunication, Guru Nanak Institution of Engineering and Technology, Nagpur, Maharashtra, India | |||||||||
Pages |
32-35 | |||||||||
Abstract |
The main objective of this paper is to provide new lower power solutions for Very Large Scale Integration (VLSI) designs. Specially, this paper focuses on the reduction of the power consumption. In this paper, we have designed pass gate adder circuit by using different pass transistor logic like CPL (Complementary Pass Transistor Logic), DCVSPG (Differential Cascade Voltage Swing Pass Transistor Logic), SRPL (Swing Restore Pass Transistor Logic), EEPL (Energy Economized Pass Transistor Logic), Push – Pull Pass transistor Logic (PPL), and Single – Ended Pass Gate Logic (SEPG). The performance of this adder circuits are compared in terms of power consumption. These circuits are designed and stimulated using Microwind 3 software. Keywords- Pass Gate Adder, Pass Transistor, Power Consumption,Microwind 3 software. | |||||||||
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