DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-1 ( Jan, 2015 ) | |||||||||
Paper Title |
FPGA Based Design And Implementation Of Convolutional Encoder And Adaptive Viterbi Decoder | |||||||||
Author Name |
M. Tulasiram, S. Venkatakiran | |||||||||
Affilition |
P.G Student, VLSI Design, Dept of ECE, 2. Associate Professor, Dept of ECE. Sri Venkatesa Perumal College of Engineering and Technology, RVS Nagar, Puttur, A.P. India | |||||||||
Pages |
16-21 | |||||||||
Abstract |
In recent years the digital wireless communications increased in this communications signal will be transmitted through channel in this transmission transmitted signal is corrupted mainly by Additive white Gaussian noise (AWGN). Convolutional encoding is considered to be one of the forward error correction schemes. A new type of coding, called Viterbi coding, can achieve a level of performance that comes closer to theoretical bounds than more conventional coding systems. The Viterbi decoder is used in high speed implementation due to non -linearity and recursive. This paper will describe the concept of the Viterbi algorithm. The Viterbi algorithm (VA) is mainly employed to decode the convolutional codes. Encoder has less complexity than the decoder. Present design of an Adaptive Viterbi Decoder (AVD) that uses survivor path with parameters for wireless communication in an attempt to reduce the power and cost and at the same time increase in speed. Viterbi Algorithm (VA)requires an exponential increase in hardware complexity to achieve greater decode accuracy. constraint length associated with the input bits are large, hence it needs to implement the larger constraint length with lesser hardware and lesser computations for decode the original data. When the decoding process uses the Modified Viterbi Algorithm (MVA) computations 50% reduced and reduction in the hardware utilization, which follows the maximum- likelihood path. It shows with the modified Viterbi decoder implementation using Xilinx 14.4 tool in verilog design. An implementation on Field Programmable Gate Arrays (FPGA) provides user flexibility to a programmable solutions and lowering the cost. | |||||||||
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