Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
Journal Home Volume Issue |
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Issue |
Volume-7,Issue-6 ( Jun, 2019 ) | |||||||||
Paper Title |
A Study on The Effect of Source-Drain Length on Device Characteristics of Junction less Transistor | |||||||||
Author Name |
Kaushik Chandra Deva Sarma | |||||||||
Affilition |
Department of Instrumentation Engineering, CIT, Kokrajhar, Assam, India | |||||||||
Pages |
11-13 | |||||||||
Abstract |
This paper presents a study on the effect of source-drain length on the performance of a symmetric double gate junction less transistor. The comparison for electrical characteristics of the device is done for different values of source-drain length by extensive simulation in TCAD. The simulation study shows that the structure with shorter source-drain region posses higher Ion/Ioff ratio and higher on current. However, effect of DIBL will be more in the device with shorter sourcedrain length. Keywords - JLT, Double Gate, Source-drain Length, Symmetric. | |||||||||
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