DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-11 ( Nov, 2014 ) | |||||||||
Paper Title |
High Performance Adaptive Binary Arithmetic Coder Used In SPIHT | |||||||||
Author Name |
Smitha Mariam Chacko | |||||||||
Affilition |
PG Scholar, Dept of Electronics and communication, Sree Buddha College of Engineering, Pattoor | |||||||||
Pages |
61-66 | |||||||||
Abstract |
The CABAC design is based on the key elements ofbinarization, context modeling, and binary arithmetic coding. Binarization makes efficient binary arithmetic coding via a unique mapping of nonbinary syntax elements to a sequence of bits, which are called bins. Each bin can either be processed in the regular coding mode or the bypass mode. The latter is chosen for selected bins in order to allow a speedup of the whole encoding (and decoding) process means of simplified non adaptive coding benefit, where a bin may be context modeled and subsequently arithmetic encoded. A pipeline register is inserted between context memory and the binary arithmetic decoder to reduce the critical path of the loop. The speed of the SPIHT algorithm is increased by using CABAC then using Arithmetic Coder. The Coding is done in VHDL language and synthesized using Xilinx ISE 13.2 and simulated using ISim. As a design decision, the speed of the SPIHT algorithm is increased by using CABAC than using Arithmetic Coder. | |||||||||
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