DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-11 ( Nov, 2014 ) | |||||||||
Paper Title |
Memory Efficient High Speed Lifting Based VLSI Architecture For Multi-Level 2d-Dwt | |||||||||
Author Name |
M.Sravanthi, T.Prasad | |||||||||
Affilition |
P.G Student in VLSI, Department of E.C.E, SIETK, Tirupati Assistant Professor, Department of E.C.E, SIETK, Tirupati | |||||||||
Pages |
20-25 | |||||||||
Abstract |
This paper proposes an improved version of lifting-based Discrete Wavelet Transform (DWT). The lifting based DWT architecture has the advantage of lower computational complexities transforming signals with extension and regular data flow. The main feature of the lifting based DWT scheme is to break up the high pass and low pass filters into a sequence of upper and lower triangular matrices and convert the filter implementation into banded matrix multiplications. Such a scheme has several advantages, including “in-place” computation of the DWT, integer-to-integer wavelet transform (IWT), symmetric forward and inverse transform, etc. In order to assess the feasibility and the efficiency of the proposed scheme, the architecture thus designed is simulated and implemented on a field-programmable gate-array board. It is therefore a challenging problem to design an efficient VLSI architecture to implement the DWT computation for real-time applications. | |||||||||
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