DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-7 ( Jul, 2018 ) | |||||||||
Paper Title |
An All-Digital CMOS Area-Efficient Delay Line | |||||||||
Author Name |
Yen-Cheng Chen, Chun-Chi Chen | |||||||||
Affilition |
Dept. of Electronic Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan | |||||||||
Pages |
62-65 | |||||||||
Abstract |
An all-digital CMOS area-efficient delay line by using a pulse-shrinking scheme is presented for time measurement. The previous mechanism applied in the all-digital delay line adopts a short channel length of the transistor to achieve a high time resolution. However, the delay time of the time-measurement delay line is short to result in a narrow dynamic range. To widen the range, the longer delay line is required to increase the circuit area considerably. The presented all-digital pulse-shrinking scheme achieves a significant improvement in resolution. Thus, a long length of the transistor is used to improve the range considerably and reach a high resolution. The delay lines with different channel lengths were implemented in a TSMC 0.35-μm CMOS process for verification. The result shows that a significant improvement in cost and a high resolution were achieved by using the presented scheme. Keywords- CMOS, Pulse Shrinking, Time Measurement, Delay Line. | |||||||||
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