DOIONLINE 
DOIONLINE Publish In |
International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)-IJIEEE |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-9 ( Sep, 2014 ) | |||||||||
Paper Title |
Design Of Low Power 4-Bit BCD Adder Using Reversible Gates | |||||||||
Author Name |
C.Mounesh Kumar, M.Srinivasulu, S.Ahmed Basha, K.Suvarna, H.Devanna | |||||||||
Affilition |
M.tech VLSISD student, SJCET, Associate Professor ECE Dept, SJCET, Assistant Professor ECE Dept SJCET, Associate Professor ECE Dept, SJCET, Associate Professor ECE Dept, SJCET | |||||||||
Pages |
14-16 | |||||||||
Abstract |
Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. The proposed BCD adder is efficient in terms of power dissipation. Various technologies are going to be used and respective power dissipation will be compared. Logic Gates such as AND, OR, NAND (Except NOT) gates are not reversible that is inputs cannot be recovered from the output. On the other hand, in Reversible Logic Gates inputs can be recovered completely from the output that is there is one to one mapping between inputs and outputs. Reversible logic gates use less power compared to classical gates and under ideal condition. | |||||||||
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