DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Special Issue-1 ( Apr, 2015 ) | |||||||||
Paper Title |
Implementation Of Parallel CRC Generation For High Speed Application | |||||||||
Author Name |
Kiran U. Mane, Pr.R.M.Khaire | |||||||||
Affilition |
Dept. of Electronics, BVDUCOEP, Pune, India Dept. of Electronics, BVDUCOEP, Pune, India | |||||||||
Pages |
128-130 | |||||||||
Abstract |
In data communication there is technology named as “data transmission”. So in data transmission cyclic redundancy check (CRC) is very needful method for detecting transmission error. By the help of recursive formula in serial CRC, it is possible to find out the parallel CRC architecture. A Serial CRC calculation cannot initiate a high throughput while parallel CRC calculation can increase the throughput of CRC computations. Proposed CRC algorithm is designed for 32-bit which can be simulated on Xilinx tools using VHDL language. Its hardware implementation is possible on FPGA board of Spartan 6 families. The design is done with the help of encoder and decoder for the serial data transmission and reception of CRC. Keywords— CRC, VHDL, Xilinx | |||||||||
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