DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-12 ( Dec, 2014 ) | |||||||||
Paper Title |
Low Power FGMOS Current-Mode Multiplier Circuits With Applications In Analog Signal Processing | |||||||||
Author Name |
Abirami N, Vijayalakshmi M, Viji K, J Shafiq Mansoor | |||||||||
Affilition |
M.E- VLSI Design, Karpagam University, Coimbatore Assistant Professor, Department of Electronics and Communication Engineering, Karpagam University Coimbatore | |||||||||
Pages |
23-26 | |||||||||
Abstract |
The current mode analog multiplier circuit using floating gate MOS (FGMOS) transistors operating in saturation region is presented. Since FGMOS stores charge for long period of time, the presented structure have the advantage of low supply voltage and low power consumption. The squaring characteristics of MOS transistor improve frequency response and the bandwidth of a multiplier. The proposed structure is designed for implementing in 180-nm CMOS technology in cadence virtuoso environment. The circuit’s power consumption and supply voltage is about 47.26 µw and 1v respectively. Keywords- Current-Mode Operation, Floating Gate Mos, Multiplier, Translinear Loop. | |||||||||
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