DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
||||||||
Issue |
Volume-5,Issue-9 ( Sep, 2017 ) | |||||||||
Paper Title |
Design, Comparision and UVM Based Verification of Encoder Architectures for Protracted Polar Codes | |||||||||
Author Name |
Surabhi B | |||||||||
Affilition |
M. Tech in VLSI design and embedded systems, Department of ECE, RVCE, Bangalore, India | |||||||||
Pages |
32-35 | |||||||||
Abstract |
The channel achieving capacity of polar codes is one of the main reasons for the popularity of polar codes. The codes of long bit width are called protracted polar codes. They find application in designs that operate on long bit widths. Protracted polar codes have proven to be very efficient in error correcting capability. There is architecture present to encode polar codes. The existent design is intuitive and is easy to implement. But the VLSI perspective of the conventional encoder is not practical as area and power consumption is more. So a partially parallel polar encoder design is implemented in order to reduce the power consumption and also reduce the number of cells used in the design. The conventional and partially parallel polar encoders are implemented and are also verified in UVM based verification environment. Keywords - Polar Encoder, Protracted Polar Codes, Universal Verification Methodology (UVM). | |||||||||
| View Paper | ||||||||||
