DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-9 ( Sep, 2017 ) | |||||||||
Paper Title |
ASIC Implementation of Nand Flash Controller | |||||||||
Author Name |
Venkata Swathi.A, I.B.K.Raju | |||||||||
Affilition |
Department of ECE, B V Raju Institute of Technology, Narsapur, Medak (Dt.) 502313, Telangana, India. | |||||||||
Pages |
28-31 | |||||||||
Abstract |
Flash memories are non-volatile in nature and these memories can be electrically erased and reprogrammed. Its small physical size, low power consumption, high shock resistance and high performance have made. The NAND Flash memory controller may be an internal device, built into the application processor or host, or designs can incorporate an external, stand-alone chip. The important applications of NAND flash are the highest-density memory is offered in the smallest footprint. The important applications of NAND flash are the highest-density memory is offered in the smallest footprint. The main objective of this paper work is to design and implement ASIC design flow for the NAND flash controller for SAMSUNG K9F1G08R0A NAND flash Device. It supports the reset, read ID, block erase, page program and page read commands. The read status command is supported for the program and erases operations. In this dissertation planning to perform different optimization techniques for simulation, synthesis using Synopsys tool at SAED Process Design Kit 32nm technology node. Keywords - ASIC, NAND flash | |||||||||
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