Publish In
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC
Journal Home
Volume Issue
Volume-5,Issue-8  ( Aug, 2017 )
Paper Title
Design of High Speed Cryptography using Finite Field Multiplier
Author Name
Sharon Rebba, S. Thirumala Devi
M.Tech – Scholar, Assistant Professor, Dept. of E.C.E, KKR & KSR INSTITUTE OF Technology & Sciences, Guntur, Andhra Pradesh
The process to develop a federal information processing standard for the advanced encryption algorithm to replace the data encryption standard. In this project, we proposed an efficient VLSI architecture for advanced encryption standard design methodology in order to provide a high-speed and effective cryptographic operation. High-performance and fast implementation of proposed multiplication is applied to cryptographic systems. The internal multiplier consists of three stages of operations they are pre-processing stage, carry generation stage, post-processing stage. The pre-processing stage focuses on propagate and generate, carry generation stage focuses on carry generation and post-processing stage focuses on final result. In this paper, we propose efficient and high speed architectures to implement cryptography using proposed multiplier. Cryptography is the operation in wireless communication between transmissions and receiving of data, the secured data is communicated in an unsecured channel between transmitter and receiver with high security. At the transmitter side the original data is converted in to secured sequence and at the receiver side the secured sequence is converted in to original data sequence.
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