DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-6 ( Jun, 2014 ) | |||||||||
Paper Title |
Modelling And Analysis Of Solid State Fault Current Limiter | |||||||||
Author Name |
J.P.Sharma, Vibhor Chauhan, Hr Kamath | |||||||||
Affilition |
JK Lakshmipat University, Suresh Gyan Vihar University, Malwa Institute of Technology India | |||||||||
Pages |
9-13 | |||||||||
Abstract |
Abstract- In modern power system, an increase in the growth of electrical energy demand is inevitable resulting in a corresponding increase in the short circuit in the power system. For this, Fault Current Limiter (FCL) became best option to reduce circuit breakers rated capacity and may limit the electromagnetic stress in associated equipment’s. In this paper modelling of solid state fault current limiter (SSFCL) under various fault conditions are carried out. The proposed SSFCL is implemented on 11 KV feeders. The performance of proposed SSFCL is evaluated in the forms of fault current. The simulation results reveal the applicability of SSFCL. The evaluation is done on MATLAB/Simulink. | |||||||||
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