DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-3 ( Mar, 2017 ) | |||||||||
Paper Title |
A New Design Method For Unbiased Finite Memory Digital Phase-Locked Loop | |||||||||
Author Name |
Sung Hyun You, Jeong Hoon Kim, Hong Bae Jeong, Choon Ki Ahn | |||||||||
Affilition |
School of Electrical Engineering, Korea University ysh88, automobile, wantyou01 | |||||||||
Pages |
1-3 | |||||||||
Abstract |
In this paper, we presented the design method for the unbiased finite memory digital phase-locked loop (UFMDPLL). We analyzed the characteristic of relation between horizon size and noise covariances of the UFMDPLL by introducing the horizon equation. The horizon equation, which is a function of horizon size N and noise covariances, is derived from error variance and ensuring unbiasedness property. Through simulations, we present the effects of among the noise covariances on the optimal horizon size of UFMDPLL. Index Terms— Digital phase-locked loop(DPLL), zero-crossing DPLL, finite, unbiased finite memory filter, unbiasedness property | |||||||||
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