DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-2 ( Feb, 2017 ) | |||||||||
Paper Title |
A Novel Design of Power and Area Optimization For 4x4 Booth Multiplier Using 180nm Technology | |||||||||
Author Name |
Sudhakar Alluri, B.Rajendra Naik, N.S.S.Reddy, Ravindra Kumar Niranjan | |||||||||
Affilition |
Department of ECE, UCE Osmania University Hyderabad, India Department of ECE, VCE Osmania University Hyderabad, India, DLRL,Hyderabad, India | |||||||||
Pages |
61-67 | |||||||||
Abstract |
In Very-large-scale integration (VLSI) application area, delay and power are the important factors for any digital circuits. This paper presents four bit 4x4 Booth Multiplier mapped in Cadence Encounter(R) RTL Compiler Version v14.20- s013_1. By efficiently mapping into cadence tool, area, power and delay are decreased. The results of mapping are viewed using RTL synthesis tool in cadence VIRTUOSO at 180 nm technology, 1.8V. Based on digital signal processing (DSP) architectures, the code for low power is generated using 4x4 Booth Multiplier. Key words- High-Level Synthesis, 4x4 Booth Multiplier, low power, low area, delay, DSP, VLSI. | |||||||||
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