DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-5,Issue-2 ( Feb, 2017 ) | |||||||||
Paper Title |
Comparison Study of 1- Bit Full Adder Design Using Different Technologies | |||||||||
Author Name |
Shikha Singh, Ashutosh Kumar Singh | |||||||||
Affilition |
M. Tech (VLSI Design), NIET Greater Noida, India Assistant Professor (ECE), NIET Greater Noida, India | |||||||||
Pages |
40-44 | |||||||||
Abstract |
The adder is an important unit in any processor and controller circuit. There are so many full adder circuits which have been proposed and designed. In this proposed work a 1-bit hybrid full adder circuit using Complementary Pass Transistor Logic and Transmission Gate Logic is designed and then compared with the existing designs such as C-CMOS, CPL,24-T full adder, TGL, Transmission Function Adder and hybrid full adder using C-CMOS and TGL logic designs. Comparative descriptions of various parameters like propagation delay, power consumption and Power Delay Product have been done. The result shows that delay is reduced by 68.037%, average power reduced by 18.90% and PDP is reduced by 12.84%. Keywords— XOR gate, Transmission Function Adder, Complementary CMOS. | |||||||||
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