DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-5 ( May, 2014 ) | |||||||||
Paper Title |
Area Efficient Implementation Of GF (2m) Multipliers For Finite Fields | |||||||||
Author Name |
Sonia Sophia Joseph, S Prakash | |||||||||
Affilition |
PG Scholar, Applied Electronics, Jerusalem College of Engineering, Chennai, India. Professor, E.C.E Department, Jerusalem College of Engineering, Chennai, India. | |||||||||
Pages |
16-18 | |||||||||
Abstract |
Abstract— Galios field arithmetic have many applications in cryptography and other fields. Multiplication is the most expensive operation in Galios field. Multipliers for Galios Field, GF (2m) have wide applications in Cryptography and error control coding systems. The existing multipliers for Galios Field require large area and time complexity, which is undesirable for real time applications. This paper presents an area-time efficient systolic structure for multiplication over GF (2m) based on irreducible all-one polynomial (AOP). A novel cut-set retiming is used to reduce the critical path to one XOR delay. The systolic structure can be further divided into two or more parallel branches to reduce the delay. The multiplier is synthesized using Verilog HDL. Area can be further reduced using a novel register sharing technique. The result shows that this multiplier has reduced area-time complexity than the existing multipliers. | |||||||||
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