DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-3 ( Mar, 2014 ) | |||||||||
Paper Title |
Finfet Based Sram Design For Low Power Applications | |||||||||
Author Name |
Shruti Oza | |||||||||
Affilition |
BVU College of Engineering, Pune-43 | |||||||||
Pages |
95-100 | |||||||||
Abstract |
Abstract- Industry demands Low-Power and High- Performance devices now-a-days. Among the various embedded memory technologies, SRAM provides the highest performance along with low standby power consumption. In CMOS circuits, high leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation due to reduction in threshold voltage, channel length, and gate oxide thickness. FinFET based SRAM design can be used as an alternative solution to the bulk devices. FinFET is suitable for nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current. As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics.The paper focuses on study of various design aspects of FinFET based SRAM | |||||||||
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