DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-4,Issue-7 ( Jul, 2016 ) | |||||||||
Paper Title |
Signal Integrity Fault Modeling And Filtering In Ultra-High-Speed SOCS For Long Interconnection | |||||||||
Author Name |
Divyansh Jain, Vibha Dhurve, Akanksha Dixit | |||||||||
Affilition |
Student, Department of Electronics and Communication, Gyan Ganga College of Technology, Rajeev Gandhi Technical University, Jabalpur, India Asst. Professor, Department of Electronics and Communication, Gyan Ganga College of Technology, Rajeev Gandhi Technical University, Jabalpur, India Asst. Professor, Department of Electronics and Communication, Shri Ram Institute of Technology, Rajeev Gandhi Technical University, Jabalpur, India | |||||||||
Pages |
50-52 | |||||||||
Abstract |
As feature sizes shrink and clock frequencies increase for high-performance system-on-a-chip (SOC) designs, signal integrity (SI), that is, the ability of an input signal to generate correct responses in a circuit is becoming a major concern for the interconnects between embedded cores As we approach 180nm technology the interconnect issues are becoming one of the main concerns in the testing of GHZ system on chip. This is achieved by considering the effect of inputs and parasitic RLC element of the inter connect. Voltage distortion (noise) and delay violation (skew) contribute to the signal integrity loss, ultimate functional error and reliability problems. Use the BIST-based test methodology to detect it. Keywords- VLSI- Very Large Scale Integration, BIST Methodology, SI , system-on-chip, interconnect testing Region and Signal Victim. | |||||||||
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