DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-4,Issue-7 ( Jul, 2016 ) | |||||||||
Paper Title |
FPGA Based Chirp Generator Using Memory Based Technique | |||||||||
Author Name |
Ravikanth Pamidi, Suma K V | |||||||||
Affilition |
Department of Electronics and Communication, M.S. Ramaiah Institute of technology, Bengaluru | |||||||||
Pages |
8-11 | |||||||||
Abstract |
The following content describe the generation of chirp signal using Memory Based Technology. The required parameters to generate chirp signal are received by the system through RS-232 serial communication protocol. Based on the input parameters FPGA generate the Chirp signal matches the input parameters. Keywords— FPGA, Chirp Signal, Memory Based Technique. | |||||||||
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