DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-7 ( Jul, 2015 ) | |||||||||
Paper Title |
High Speed Low Power Asic Design Of Multiplier Using Vedic Mathematics | |||||||||
Author Name |
Navyashree Hosamane, G.Jyothi, M Z Kurian | |||||||||
Affilition |
M.Tech student (VLSI& Embedded System), SSIT, Tumkur, Karnataka Assistant Professor, Dept of ECE, SSIT, Tumkur, Karnataka H.O.D, Dept of ECE, SSIT, Tumkur, Karnataka | |||||||||
Pages |
78-81 | |||||||||
Abstract |
the performance of any processor will mainly depend upon its power and delay. The power and delay should be less in order to get a high performance .Multipliers are the basic building blocks in almost all processors. Hence, there is a need for highly efficient and sophisticated multiplier. The need of efficient multiplier is to increase the processing speed of the system in real time signal and processing applications. A high speed low power multiplier design (ASIC) using Urdhva and Nikhilam sutra ofVedic mathematics is presented in this paper. The proposed urdhva and nikilam multipliers achieve 60%, 77% improvement in speed and 37%, 50% improvement in power respectively, as compared with that of conventional array multipliers. Keywords: Vedicmultiplier; Arraymultiplier; Urdhva;Nikhilam | |||||||||
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