DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-7 ( Jul, 2015 ) | |||||||||
Paper Title |
Design Of A Large Signal Memory Array For High Frequency Microprocessors | |||||||||
Author Name |
Ruchika Mishra, Rajendra Prasad | |||||||||
Affilition |
Dual Degree M.Ttech(5th year) , School of Electronics Engineering, KIIT University, Bhubaneswar Assistant Professor , School Of Electronics Engineering KIIT University Bhubaneswar | |||||||||
Pages |
53-56 | |||||||||
Abstract |
This paper focuses on designing an 80 bit 160 entry Register File for uncore applications like Cache controller, DRAM controller, Hard disk controller and Integrated graphics controller rather than the core instructions or data. The main objective is to develop a methodology to optimize the LSA in area, performance, power, robust to noise and be able to perform in low voltage conditions. This is done by determining the characterization results of Read and Write word line drivers and Bit line drivers. The characterization results are obtained using Cadence RTL Compiler . Keywords – Bit line driver, Memory cell, Register File, Word line driver. | |||||||||
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