DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-7 ( Jul, 2015 ) | |||||||||
Paper Title |
Improved Analytical Modeling For Junctionless Transistor | |||||||||
Author Name |
Vikkee, Ashutosh Nandi | |||||||||
Affilition |
School of VLSI and Embedded System, NIT kurukshetra, INDIA, Department of Electronics and Communication, NIT Kurukshetra, INDIA | |||||||||
Pages |
42-44 | |||||||||
Abstract |
In this paper, we have derived and proposed an analytical model of junctionless transistor by solving poisson equation with variable separation method. The 2-D poisson equation in both silicon and oxide regions are solved to deduce expressions of surface potential, threshold voltage and drain induced barrier lowering of double gate junctionless transistor. Behavior of Derived expression is compare with analytical model of junctionless DG-MOSFET and TCAD sentaurus results. Proposed results give good agreement with these results. Index Terms- Junctionless transistor, 2-D poisson equation, surface potential, Short channel effect (SCE), Drain Induced Barrier Lowering (DIBL). | |||||||||
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