DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-7 ( Jul, 2015 ) | |||||||||
Paper Title |
Performance Improvement Of A Modified Carry Select Adder | |||||||||
Author Name |
Aritra Mitra Amit Bakshi | |||||||||
Affilition |
25th Year Dual Degree M.Tech KIIT University, Assistant Professor KIIT University | |||||||||
Pages |
39-41 | |||||||||
Abstract |
This paper contains various performance improvement techniques of a modified architecture of carry select adder. The conventional Carry Select Adder is first designed and then modification is done to improve performance parameters such as delay reduction, power dissipation, power Delay Product. We simulated these designs along with a modified design in cadence VIRTUOSO environment in 180nm CMOS technology and compared their performance parameters are compared. Keywords – CMOS Logic, Carry Select Adder, GDI Approach, High Performance | |||||||||
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