DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-1,Issue-8 ( Oct, 2013 ) | |||||||||
Paper Title |
Loading Of Machine Code At Run Time For Soft-Core Processor On FPGA | |||||||||
Author Name |
R. Arokia Priya, Priyanka Balu Bhor | |||||||||
Affilition |
Assistant Professor, D.Y Patil College Of Engineering,Akurdi | |||||||||
Pages |
63-65 | |||||||||
Abstract |
Application specific customization nowadays can be very well achieved by implementing soft-core processor on FPGA’s. But if any changes are to be made to the assembly codes of the implemented processor it is required to reimplement and again download the soft-core. Here is a technique to implement a run time loading technique for a MIPS processor. This proposed design consists of three main blocks: a UART soft-core, a software tool, soft-core processor. UART soft core used in the proposed design will be superior to the conventional one, because it willbe customizable as well as will also indicate the error type if any error occurs during the transmission of data. The assembly code generated and compiled by the software will be sent through UART to the CPU implemented on the FPGA at run time | |||||||||
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