DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-12,Issue-6 ( Jun, 2024 ) | |||||||||
Paper Title |
Implementation Of Rounding Technique In Posit Multiplier Design For Signed And Unsigned Data | |||||||||
Author Name |
Divyalakshmi.K, Bharath.B, Karthik Reddy.C, Shafikha.B,Venkata Anuhya.C, Vamsi.G | |||||||||
Affilition |
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Pages |
18-23 | |||||||||
Abstract |
In contrast to conventional floating-point arithmetic, posit arithmetic is a novel method of expressing numbers that is explored in this study. Its goal is to be more flexible and efficient. It's especially crucial in digital systems where efficiency and precision are essential. The three primary components of the paper are Working with 16-bit values, the adder and multiplier employ a variety of factors in their computations to guarantee correct alignment and add requirements for precise outcomes. Both the adder and multiplier are tested using theposit testbench, which also adds delays to replicate realworld situations and evaluates the adder's performance under various scenarios. When posit arithmetic is contrasted with standard arithmetic, it provides more precision and a larger range, particularly in complicated computations. It is made to be more accurate across a range of values and to better manage rounding mistakes. Because of this, posit arithmetic is appropriate for high-performance computing and machine learning applications where efficiency and accuracy are critical. Keywords - Posit,unum (universal number system), rounding-based approximation (RoBA) | |||||||||
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