DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-11,Issue-5 ( May, 2023 ) | |||||||||
Paper Title |
Design of Floating-Point Multiplier for Logic and Power Optimization: A Review | |||||||||
Author Name |
Sampath Kumar V, Rashika Anurag, Khushi Sangal, Sanyam Jain, Shristi Bharti | |||||||||
Affilition |
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Pages |
32-37 | |||||||||
Abstract |
Floating-point representation of any fractional number offers a wider dynamic range which makes it extremely compliant and scalable against fixed-point representation. Since fractional numbers are frequently used in computation, such as in astronomical calculations, graphics processing, and signal processing, floating-point representation becomes the ideal representation for them. Floating-point multipliers perform differently depending on the multiplier design. The purpose of this paper is to review various studies done in the field of floating-point multipliers, such as the Modified Booth multiplier, Array multiplier, Dadda multiplier, Wallace Tree multiplier, and Vedic multiplier. A floating-point multiplier's performance is evaluated based on a number of attributes, including speed, latency, area, and power consumption. In the design phase, Verilog HDL is used, and in the simulation phase, Xilinx Isim is used. To implement RTL blocks created with Xilinx ISE 14.7, FPGA devices were used. Keyword - Floating-point Numbers, Single-precision (32-bit), Double-precision (64-bit), IEEE-754, Array, Modified Booth, Wallace tree, Dadda tree, Vedic, Verilog HDL, Xilinx ISE, FPGA. | |||||||||
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