DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-10,Issue-7 ( Jul, 2022 ) | |||||||||
Paper Title |
An Area Efficient Design of MIDORI-64 for IOT Applications | |||||||||
Author Name |
Aakanksha Baghel, Zeesha Mishra, Onika Parmar, Amit Singh Rajput | |||||||||
Affilition |
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Pages |
97-102 | |||||||||
Abstract |
Abstract - Modern cryptographic algorithms are the backbone of data security and privacy for highly confidential and classified information. The Internet of Things (IoT) is a system of interconnected devices which share data and information in real time. The growing number of linked devices in IoT applications has raised serious security problems. Lightweight cryptographic algorithms seem to be the solution for the challenge of providing security solutions to resource-constrained devices. Midori is one such algorithm which follows SPN structure. Midori is available in two block sizes namely 64-bit and 128-bit, both uses 128-bit key size. The proposed designs are implemented in verilog HDL using Xilinx ISE Design suite. Comparison with different families of FPGA has been done. There is a improvement of 20.33% in area (slices), and 50.29% in throughput. Keywords - Cryptography, LWC, Midori, FPGA, Slices, Throughput | |||||||||
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