DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-10,Issue-7 ( Jul, 2022 ) | |||||||||
Paper Title |
Independent Gate TFETS for Logic Realization: A Review | |||||||||
Author Name |
Sourav Kumar Biswal | |||||||||
Affilition |
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Pages |
72-75 | |||||||||
Abstract |
Abstract - Independent gate tunnel FETS have the potential to replace Cmos logic which can have less area by reducing number of transistor required to implement a logic and can operate on low voltages. Independent gate devices with strong coupling between back and front gates can generate different logic by using different device threshold voltages, which can reduce the number of transistors used in circuits. In this article we have discussed the various device structure and techniques available to optimizetheindependentgateTFETtoachievefunctionalitysimilartoaCmosAND,ORlogicgate. Keywords - IG TFET, Ambipolar Current, Logic Realization in TFETs | |||||||||
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