DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-10,Issue-6 ( Jun, 2022 ) | |||||||||
Paper Title |
State of The Art Low Noise Amplifier Topologies Proposal of A Tunable LNA Design | |||||||||
Author Name |
Rajni Parashar, Garima Kpaur | |||||||||
Affilition |
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Pages |
40-45 | |||||||||
Abstract |
Abstract - This paper presents thecase study on different design topologies, design parameters and the design issues that should be considered while designing a low-noise amplifier(LNA). The paper also proposes a gyrator-based CMOS Active inductor (AI) whose inductance value and operating frequency is tunable post fabrication. The same can be used to implement a tunable LNA CMOS based design which in turn can be used in Radio Frequency Integrated Circuit(RFIC) designs. The recent development of AI based LNA and the methods of tuning has also been described briefly.The Tunable AI inductance can be tuned from 3nH to 9nH with self-resonating frequency tuned in the range of 800MHz to 1.2GHz using external bias voltages. The same when employed in LNA design, gain and operating frequency can be tuned which in turn will be very helpful to develop a RFIC whose operating frequency can be tuned after fabrication, thus such RFIC can find wide range of application like Bluetooth, Wi-Fi hardware etc. Keywords - RFIC, LNA topologies, AI base LNA, tuning of LNA | |||||||||
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