DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-9,Issue-8 ( Aug, 2021 ) | |||||||||
Paper Title |
Advanced TCAM Design Using SRAM | |||||||||
Author Name |
M.Hanumanthu, P.Geetha, P.Maneesha, E.V.R.Saranya, S.Prathyusha | |||||||||
Affilition |
Assistant Professor, Department Technology of ECE, Annamacharya Institute of Technology and Sciences, Rajampet Undergraduate in ECE, Annamacharya Institute of Technology and Sciences, Rajampet Undergraduate in ECE, Annmacharya Institute of and Sciences, Rajampet Undergraduate in ECE, Annamacharya Institute of Technology and Sciences, Rajampet Undergraduate in ECE, Annamacharya Institute of Technology and Sciences, Rajampet, A.P, India. | |||||||||
Pages |
19-22 | |||||||||
Abstract |
Ternary content-addressable reminiscences (TCAMs) square measure won‟t to style high-speed search engines. TCAM is enforced on application-specific computer circuit (native TCAMs) and field-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs) platforms however each have the downside of higher power consumption. This paper presents a pre-classifier-based design for AN energy-efficient SRAM-based TCAM. the primary classification stage divides the TCAM table into many sub-tables of balanced size. The second SRAM-based implementation stage maps every of the resultant TCAM sub-tables to a separate row of organized SRAM blocks within the design. The projected design by selection activates at the most one row of SRAM blocks for every incoming TCAM word. Compared with the present SRAM-based TCAM styles on FPGAs, the projected style consumes considerably reduced energy because it activates an area of SRAM memory used for operation instead of the complete SRAM memory as within the previous schemes. we have a tendency to enforced the projected approach sample styles of size 512 × 36 on Xilinx Virtex-6 FPGA. The experimental results showed that the projected style achieved a minimum of 3 times lower power consumption per performance than different SRAM-based TCAM architectures. | |||||||||
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