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International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC
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Volume Issue
Volume-9,Issue-8  ( Aug, 2021 )
Paper Title
Design of a 16-Bit Harvard Structured Risc Processor using Cadence 45nm Technology
Author Name
C H Nagaraju, L.Harshitha, S.Althaf, C.Yogitha, B.Mallikarjuna Reddy, C.Venkata Sahithi
Professor, Head of the Department, Department of ECE, Annamacharya Institute of Technology and Sciences, Rajampet Undergraduate in ECE, Annamacharya Institute of Technology and Sciences, Rajampet
The architecture of a MIPS (Microprocessor without Interlocked Pipeline Stages) based RISC or Reduced Instruction Set of Computers is a type of microprocessor which was designed by Harvard type data path structure to execute high speed using a small set of Instructions. This project explains the design and implementation of a 4-stage pipelining based low power processor. This feature leads to increase the reliability and speed of the system. The pipelining includes fetch, decode, execute and memory read/write operations. Low power was obtained by using clock gating technique. Clock gating is used to eliminate the unwanted clock usage when the module is not used. The main aim of the project is to design a 4-stage pipelined RISC processor starting from RTL to GDSII (Physical Design). The processor was coded by Verilog HDL language and implemented in Cadence Encounter Compiler tool. Calculated area, power, delay and clock gating using Cadence RTL compiler using slow and fast libraries of 45nm technology. Keywords - RISC, MIPS, RTL (Register Transfer Logic), GDSII (Graphic Design System for Information Interchange a Gerber File), Cadence Encounter Compiler, 4- stage Pipeline, Physical Design.
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