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International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC
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Volume Issue
Volume-7,Issue-10  ( Oct, 2019 )
Paper Title
Comparative Study of SPI Design Systems
Author Name
Vimal Kumar Verma
M.Tech. Student Dept. of ECE Greater Noida Institute of Technology, Greater Noida, India
There's a specialized chip-selection signal used for addressing and controlling an individual slave in most frequent SPI schemes with one master and several slaves arrangement that we can meet when design. But the complication of such a scheme is that if the number of slaves increases in the circuit, there are also more chip-select lines and the circuit becomes complex and this is difficult to design. In such a situation, maintaining the minimality of the design becomes a challenge. A developer can use other techniques, such as daisy chaining with fewer terminals on the master computer but with the significant lack of a small bandwidth for communication. A comprehensive comparison research with general SPI and Daisy-chained SPI systems is described in this paper. Keywords - Intellectual Property Core, Serial Communication, Serial Peripheral Interface, SOC
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