DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
||||||||
Issue |
Volume-7,Issue-9 ( Sep, 2019 ) | |||||||||
Paper Title |
Effective Design and Verification of AHB using System Verilog | |||||||||
Author Name |
Akhila M L, Shaik Chand Basha | |||||||||
Affilition |
PG Student, Department of ECE, NMAMIT, NITTE, Karkala, India Design Verification Engineer, Sion Semiconductors Pvt.Ltd., Bangalore, India | |||||||||
Pages |
74-78 | |||||||||
Abstract |
Day by day, electronic elements are becoming smaller in size, with higher performance and high operating range. All this is possible because of System-on-Chip architecture where multiple blocks are integrated in a single IC. ARM introduced AMBA architecture, which speeds up on-Chip bus communication. Advanced Microcontroller Bus Architecture includes several bus architectures like APB, ASB and AHB. Among them Advanced High-Performance Bus Architecture is the first choice for chip designers due to its high performance features. Creating verification environment is important to check if the DUT meets the specification. Effective design and verification environment of Advanced High-Performance Bus using System Verilog is presented in this paper. Also, the functional verification of AHB with burst transfers, address and data phase pipelining, sequential and non-sequential transfers are done. QuestaSim tool is used for designing and functionally verifying the design. Keywords - AHB, AMBA, Master, Slave, SoC, Boundary Address, DUT, System Verilog. | |||||||||
| View Paper | ||||||||||
